Digital logic circuits often rely on clock signals for synchronization, derivation of reference signals, measuring phase differences, and other functions. The circuits may be segregated into different integrated circuits or different subsystems of a larger electronic device.
One approach for getting the clock signal to components is to distribute the clock signal from a centralized clock to every component requiring the clock signal. One disadvantage of this approach is that clock signals tend to have constraints that are difficult to maintain when the distribution is over a relatively large area or used to drive a relatively large number of components.
Another technique for distributing a clock signal entails distributing a reference clock signal to different components or even different regions within an integrated circuit. Each component or region has a local phase locked loop (PLL) or local delay locked loop (DLL) buffer to derive one or more local clock signals from the reference clock signal. Such designs are sometimes referred to as a “clock tree”. The use of a tree structure allows clocked buffers to be configured for the specifics of the loads they are driving as well as limiting the load to be driven by any clock signal.
A PLL is “locked” when the PLL output clock frequency (FOUT_CLK) matches and tracks the frequency of the reference clock (FREF_CLK) and the PLL output clock is maintaining a predetermined phase angle relative to that of the reference clock (typically zero). Depending upon the type of PLL, calibration is typically accomplished by searching through frequency bands until a frequency band is found that includes the frequency of the reference clock signal. Searching for the calibration band takes a finite amount of time. The calibration time impacts the overall time to initialize the system relying on the PLL. Calibration time for finding the calibration frequency band for the PLL is an important attribute of a PLL.
One prior art method of calibration uses a binary search algorithm to identify the calibration band. The prior art calibration process iteratively selects a candidate band for PLL operation. Each iteration typically eliminates half of the remaining bands as candidates for the calibration band. Given B frequency bands to search, a binary search algorithm can identify the calibration band with a worst case number of guesses on the order of log2(B) guesses, i.e., O(log2(B)). Due to the number of reference clock cycles required to accumulate a meaningful difference between the frequency of the reference clock signal and the frequency of the output clock signal this amount of time may be too long for some applications.